User RAM FIFO Registers - Advanced
Name Start Address Type Access
USER_RAM_FIFO#(0:3)_DATA_U16 47000 UINT16 R/W
USER_RAM_FIFO#(0:3)_DATA_U32 47010 UINT32 R/W
USER_RAM_FIFO#(0:3)_DATA_I32 47020 INT32 R/W
USER_RAM_FIFO#(0:3)_DATA_F32 47030 FLOAT32 R/W
USER_RAM_FIFO#(0:3)_ALLOCATE_NUM_BYTES 47900 UINT32 R/W
USER_RAM_FIFO#(0:3)_NUM_BYTES_IN_FIFO 47910 UINT32 R
USER_RAM_FIFO#(0:3)_EMPTY 47930 UINT32 W
USER_RAM_FIFO#(0:3)_DATA_U16
- Starting Address: 47000
Generic FIFO buffer. Useful for passing ORDERED or SEQUENTIAL data between various endpoints, such as between a host and a Lua script. Use up to 4 FIFO buffers simultaneously->1 of each data type, all 4 different data types, or a mixture. e.g. FIFO0_DATA_U16 points to the same memory as other FIFO0 registers, such that there are a total of 4 memory blocks: FIFO0, FIFO1, FIFO2 and FIFO3. It is possible to write into a FIFO buffer using a different datatype than is being used to read out of it. This register is a buffer. Underrun behavior - throws an error.
  • Data type: UINT16  (type index = 0)
  • Readable and writable
  • Default value: 0
  • This register is a Buffer Register
  • T8:
  • T7:
Expanded Names Addresses
USER_RAM_FIFO0_DATA_U16, USER_RAM_FIFO1_DATA_U16, USER_RAM_FIFO2_DATA_U16, USER_RAM_FIFO3_DATA_U16 Show All 47000, 47001, 47002, 47003 Show All
USER_RAM_FIFO#(0:3)_DATA_U32
- Starting Address: 47010
Generic FIFO buffer. Useful for passing ORDERED or SEQUENTIAL data between various endpoints, such as between a host and a Lua script. Use up to 4 FIFO buffers simultaneously->1 of each data type, all 4 different data types, or a mixture. e.g. FIFO0_DATA_U16 points to the same memory as other FIFO0 registers, such that there are a total of 4 memory blocks: FIFO0, FIFO1, FIFO2 and FIFO3. It is possible to write into a FIFO buffer using a different datatype than is being used to read out of it. This register is a buffer. Underrun behavior - throws an error.
  • Data type: UINT32  (type index = 1)
  • Readable and writable
  • Default value: 0
  • This register is a Buffer Register
  • T8:
  • T7:
Expanded Names Addresses
USER_RAM_FIFO0_DATA_U32, USER_RAM_FIFO1_DATA_U32, USER_RAM_FIFO2_DATA_U32, USER_RAM_FIFO3_DATA_U32 Show All 47010, 47012, 47014, 47016 Show All
USER_RAM_FIFO#(0:3)_DATA_I32
- Starting Address: 47020
Generic FIFO buffer. Useful for passing ORDERED or SEQUENTIAL data between various endpoints, such as between a host and a Lua script. Use up to 4 FIFO buffers simultaneously->1 of each data type, all 4 different data types, or a mixture. e.g. FIFO0_DATA_U16 points to the same memory as other FIFO0 registers, such that there are a total of 4 memory blocks: FIFO0, FIFO1, FIFO2 and FIFO3. It is possible to write into a FIFO buffer using a different datatype than is being used to read out of it. This register is a buffer. Underrun behavior - throws an error.
  • Data type: INT32  (type index = 2)
  • Readable and writable
  • Default value: 0
  • This register is a Buffer Register
  • T8:
  • T7:
Expanded Names Addresses
USER_RAM_FIFO0_DATA_I32, USER_RAM_FIFO1_DATA_I32, USER_RAM_FIFO2_DATA_I32, USER_RAM_FIFO3_DATA_I32 Show All 47020, 47022, 47024, 47026 Show All
USER_RAM_FIFO#(0:3)_DATA_F32
- Starting Address: 47030
Generic FIFO buffer. Useful for passing ORDERED or SEQUENTIAL data between various endpoints, such as between a host and a Lua script. Use up to 4 FIFO buffers simultaneously->1 of each data type, all 4 different data types, or a mixture. e.g. FIFO0_DATA_U16 points to the same memory as other FIFO0 registers, such that there are a total of 4 memory blocks: FIFO0, FIFO1, FIFO2 and FIFO3. It is possible to write into a FIFO buffer using a different datatype than is being used to read out of it. This register is a buffer. Underrun behavior - throws an error.
  • Data type: FLOAT32  (type index = 3)
  • Readable and writable
  • Default value: 0
  • This register is a Buffer Register
  • T8:
  • T7:
Expanded Names Addresses
USER_RAM_FIFO0_DATA_F32, USER_RAM_FIFO1_DATA_F32, USER_RAM_FIFO2_DATA_F32, USER_RAM_FIFO3_DATA_F32 Show All 47030, 47032, 47034, 47036 Show All
USER_RAM_FIFO#(0:3)_ALLOCATE_NUM_BYTES
- Starting Address: 47900
Allocate memory for a FIFO buffer. Number of bytes should be sufficient to store users max transfer array size. Note that FLOAT32, INT32, and UINT32 require 4 bytes per value, and UINT16 require 2 bytes per value. Maximum size is limited by available memory. Care should be taken to conserve enough memory for other operations such as AIN_EF, Lua, Stream etc.
  • Data type: UINT32  (type index = 1)
  • Readable and writable
  • Default value: 0
  • This register uses system RAM. The maximum RAM is 64KB. For more information, see 4.4 RAM
  • T8:
  • T7:
Expanded Names Addresses
USER_RAM_FIFO0_ALLOCATE_NUM_BYTES, USER_RAM_FIFO1_ALLOCATE_NUM_BYTES, USER_RAM_FIFO2_ALLOCATE_NUM_BYTES, USER_RAM_FIFO3_ALLOCATE_NUM_BYTES Show All 47900, 47902, 47904, 47906 Show All
USER_RAM_FIFO#(0:3)_NUM_BYTES_IN_FIFO
- Starting Address: 47910
Poll this register to see when new data is available/ready. Each read of the FIFO buffer decreases this value, and each write to the FIFO buffer increases this value. At any point in time, the following equation holds: Nbytes = Nwritten - Nread.
  • Data type: UINT32  (type index = 1)
  • Read-only
  • Default value: 0
  • T8:
  • T7:
Expanded Names Addresses
USER_RAM_FIFO0_NUM_BYTES_IN_FIFO, USER_RAM_FIFO1_NUM_BYTES_IN_FIFO, USER_RAM_FIFO2_NUM_BYTES_IN_FIFO, USER_RAM_FIFO3_NUM_BYTES_IN_FIFO Show All 47910, 47912, 47914, 47916 Show All
USER_RAM_FIFO#(0:3)_EMPTY
- Starting Address: 47930
Write any value to this register to efficiently empty, flush, or otherwise clear data from the FIFO.
  • Data type: UINT32  (type index = 1)
  • Write-only
  • Default value: 0
  • T8:
  • T7:
Expanded Names Addresses
USER_RAM_FIFO0_EMPTY, USER_RAM_FIFO1_EMPTY, USER_RAM_FIFO2_EMPTY, USER_RAM_FIFO3_EMPTY Show All 47930, 47932, 47934, 47936 Show All